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1 of 36 optimum technology matching? applied gaas hbt ingap hbt gaas mesfet sige bicmos si bicmos sige hbt gaas phemt si cmos si bjt gan hemt functional block diagram rf micro devices?, rfmd?, optimum technology matching?, enabling wireless connectivity?, powerstar?, polaris? total radio? and ultimateblue? are trademarks of rfmd, llc. bluetooth is a trade- mark owned by bluetooth sig, inc., u.s.a. and licensed for use by rfmd. all other trade names, trademarks and registered tradem arks are the property of their respective owners. ?2006, rf micro devices, inc. product description 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . rf mems ldmos ? frac-n sequence generator n divider phase / freq detector charge pump ref divider synth mixer lo divider RF2053 high performance fractional-n synthesizer with integrated rf mixer the RF2053 is a low power, high performa nce, wideband rf frequency conversion chip with integrated local oscillator (lo) generation and rf mixer. the rf synthe- sizer includes an integrated fractional-n phase locked loop that can control an external vco to produce a low-phase noise lo signal with a very fine frequency res- olution. the vco output frequency can be divided by 1, 2, or 4 in the lo divider, whose output is buffered and drives the built-in rf mixer which converts the signal into the required frequency band. the mixer bias current can be programmed dependent on the required performance and available supply current. the lo gen- eration blocks have been designed to operate with external vcos covering the fre- quency range from 300mhz to 2400mhz. the rf mixer is very broad band and operates from 30mhz to 2500mhz at the in put and output, enabling both up and down conversion. an external crystal of between 10mhz and 52mhz or an external reference source of between 10mhz and 104mhz can be used with the RF2053 to accommodate a variety of reference frequency options. all on-chip registers are controlled through a simple three-wire serial interface. the RF2053 is designed for 2.7v to 3.6v operation for compatibility with portable, bat- tery powered devices. it is available in a plastic 32-pin, 5mmx5mm qfn package. features ? fractional-n synthesizer ? very fine frequency resolution 1.5hz for 26mhz reference ? 300mhz to 2400mhz external vco frequency range ? on-chip crystal-sustaining circuit with programmable loading capacitors ? integrated lo buffer and lo divider ? high-linearity rf mixer ? mixer input ip3 +23dbm typ. ? mixer bias adjustable for low power operation ? mixer frequency range 30mhz to 2500mhz ? 2.7v to 3.6v power supply ? low current consumption 50ma to 70ma at 3v ? 3-wire serial interface applications ? catv head-ends ? digital tv up/down converters ? digital tv repeaters ? multi-dwelling units ? frequency band shifters ? uhf/vhf radios ? software defined radios ? satellite communications ? super-heterodyne radios ds140110 package: qfn, 32-pin, 5mmx5mm RF2053
2 of 36 RF2053 ds140110 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . detailed functional block diagram pin out serial data interface, control and biasing analog regulator digital regulator lo divider /1, /2, or /4 lo buffer mixer vco buffer reference divider /1 to /7 reference oscillator circuitry and crystal tuning - + vref n divider phase / freq detector frac-n sequence generator charge pump synthesizer vtune ana_vdd dig_vdd ana_dec lfilt1 vcoinp vcoinn rext xtalipp xtalipn enx enbl mode resetb sdata sclk rfopn rfopp rfipn rfipp serial bus control ana_vdd op 4:1 1:1 ip 1:1 external vco external op-amp 1 3 2 6 5 4 7 enbl vcoinp vcoinn rext ana_dec lfilt1 nc 8 nc 25 27 26 30 29 28 31 nc nc rfopn rfopp resetb enx sclk 32 sdata 24 22 23 19 20 21 18 rfipp rfipn ana_vdd nc nc dig_vdd nc 17 nc 9 11 10 14 13 12 15 mode xtalipp xtalipn gnd nc nc nc 16 nc ep
3 of 36 RF2053 ds140110 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . note 1: the signal should be connected to this pin such that dc current cannot flow into or out of the chip, either by using ac coupling capacitors or by use of a transformer (see evaluation board schematic). note 2: dc current needs to flow from ana_vdd into this pin, either through an rf inductor, or transformer (see evaluation board schematic). note 3: alternatively an external referenc e can be ac-coupled to pin 11 xtalipn, and pin 10 xtalipp decoupled to ground. this may make pcb routing simpler. pin function description 1enbl ensure that the enbl high voltage level is not greater than v dd . an rc low-pass filter could be used to reduce digital noise. 2vcoinp external vco differential input. see note 1. 3vcoinn external vco differential input. see note 1. 4rext external bandgap bias resistor. connect a 51k ? resistor from this pin to grou nd to set the ba ndgap reference bias current. this could be a sensitive low frequency noise injection point. 5ana_dec analog supply decoupling capacitor. connect to analog su pply and apply rf decoupling to a good quality ground as close to the pin as possible. 6lfilt1 phase detector output. low-frequency noise-sensitive node. 7nc 8nc 9mode mode select pin. connect to dig_vdd if mode switching is not required. 10 xtalipp reference crystal / reference oscillator input. should be ac-coupled if an external reference is used. see note 3. 11 xtalipn reference crystal / reference oscillator input. should be ac-coupled to ground if an external reference is used. see note 3. 12 gnd connect to ground. 13 nc 14 nc 15 nc 16 nc 17 nc 18 nc 19 dig_vdd digital supply. should be decouple d as close to the pin as possible. 20 nc 21 nc 22 ana_vdd analog supply. should be decoupled as close to the pin as possible. 23 rfipn differential input. see note 1. 24 rfipp differential input. see note 1. 25 nc 26 nc 27 rfopn differential output. see note 2. 28 rfopp differential output. see note 2. 29 resetb chip reset (active low). connect to dig_vdd if external reset is not required. 30 enx serial interface select (active low). an rc low-pa ss filter could be used to reduce digital noise. 31 sclk serial interface clock. an rc low-pass filter could be used to reduce digital noise. 32 sdata serial interface data. an rc low-pass filter could be used to reduce digital noise. ep exposed pad connect to ground. this is the ground reference for the circuit. all decoupling should be connected here through low impedance paths.
4 of 36 RF2053 ds140110 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . absolute maximum ratings parameter rating unit supply voltage (v dd ) -0.5 to +3.6 v input voltage (v in ), any pin -0.3 to v dd +0.3 v rf/if mixer input power +15 dbm operating temperature range -40 to +85 c storage temperature range -65 to +150 c parameter specification unit condition min. typ. max. esd requirements human body model general 2000 v rf pins 1000 v machine model general 200 v rf pins 100 v operating conditions supply voltage (v dd ) 2.7 3.0 3.6 v temperature (t op ) -40 +85 c logic inputs/outputs v dd =supply to dig_vdd pin input low voltage -0.3 +0.5 v input high voltage v dd / 1.5 v dd v input low current -10 +10 ua input=0v input high current -10 +10 ua input=v dd output low voltage 0 0.2*v dd v output high voltage 0.8*v dd v dd v load resistance 10 k ? load capacitance 20 pf static programmable supply current (i dd ) low current setting 50 ma high linearity setting 70 ma standby 3 ma reference oscillator and bandgap only. power down current 140 ? aenbl=0 and ref_stby=0 mixer mixer output driving 4:1 balun. gain -2 db not including balun losses. noise figure low current setting 9.5 db high linearity setting 12 db
5 of 36 RF2053 ds140110 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . parameter specification unit condition min. typ. max. mixer, cont. iip3 low current setting +12 dbm high linearity setting +23 dbm pin1db low current setting +2 dbm high linearity setting +12 dbm rf and if port frequency range 30 2500 mhz mixer input return loss 10 db 100 ? differential voltage controlled oscillator differential input external vco input frequency 300 2400 mhz external vco input level -6 -3 0 dbm reference oscillator xtal frequency 10 52 mhz external reference frequency 10 104 mhz reference divider ratio 1 7 external reference input level 500 800 1500 mv p-p ac-coupled local oscillator synthesizer output frequency 75 2400 mhz at lo divider output phase detector frequency 52 mhz closed loop phase-noise at 1khz offset 26mhz phase detector frequency 2ghz lo frequency -85 dbc/hz 1ghz lo frequency -91 dbc/hz 500mhz lo frequency -97 dbc/hz closed loop phase-noise at 10 khz offset 26mhz phase detector frequency 2ghz lo frequency -90 dbc/hz 1ghz lo frequency -95 dbc/hz 500mhz lo frequency -102 dbc/hz charge pump charge pump current 120 240 ? a charge pump output voltage +0.7 +1.1 +1.5 v
6 of 36 RF2053 ds140110 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . typical performance characteristics for the RF2053 synthesizer v dd =3v, t a =25c, as measured on RF2053 evaluation board, phase detector frequency=26mhz. typical performance characteristics for the RF2053 -160.0 -150.0 -140.0 -130.0 -120.0 -110.0 -100.0 -90.0 -80.0 -70.0 -60.0 0.1 1 10 100 1000 10000 phase noise (dbc/hz) offset frequency (khz) phase noise of RF2053 and ums-2150-r16 vco (wideband evb) 950mhz 1250mhz 1550mhz 1850mhz 2150mhz -160.0 -150.0 -140.0 -130.0 -120.0 -110.0 -100.0 -90.0 -80.0 -70.0 -60.0 0.1 1 10 100 1000 10000 phase noise (dbc/hz) offset frequency (khz) phase noise of RF2053 and umx-236-d16 vco (narrowband evb) at 1660mhz icp = 011111 icp = 111111 -110.0 -100.0 -90.0 -80.0 -70.0 -60.0 10 20 30 40 50 phase noise (dbc/hz) phase detector frequency (mhz) synthesizer output phase noise floor at 1khz offset versus phase detector frequency 2ghz 1ghz 0.5ghz -120.0 -110.0 -100.0 -90.0 -80.0 -70.0 10 20 30 40 50 phase noise (dbc/hz) phase detector frequency (mhz) synthesizer output phase noise floor at 10khz offset versus phase detector frequency 2ghz 1ghz 0.5ghz 40.0 45.0 50.0 55.0 60.0 65.0 70.0 75.0 80.0 001 010 011 100 101 supply current (ma) mixer bias current setting (mix2_idd) operating current versus temperature and supply voltage -40degc, +2.7v -40degc, +3.0v -40degc, +3.6v +27degc, +2.7v +27degc, +3.0v +27degc, +3.6v +85degc, +2.7v +85degc, +3.0v +85degc, +3.6v
7 of 36 RF2053 ds140110 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . typical performance characteristics for the RF2053 mixer v dd =3v, t a =25c, unless stated, as measured on RF2053 wideband evaluation board, phase detector frequency=26mhz. -10.0 -9.0 -8.0 -7.0 -6.0 -5.0 -4.0 -3.0 -2.0 -1.0 0.0 250 500 750 1000 1250 1500 1750 2000 2250 conversion gain (db) rf input frequency (mhz) RF2053 mixer conversion gain if output = 100mhz & lo = rf + if -40degc, +2.7v -40degc, +3.0v -40degc, +3.6v +27degc, +2.7v +27degc, +3.0v +27degc, +3.6v +85degc, +2.7v +85degc, +3.0v +85degc, +3.6v 0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 250 500 750 1000 1250 1500 1750 noise figure (db) rf input frequency (mhz) mixer noise figure versus rf input frequency if = 100mhz, +27deg c and +3.0v supply mix2_idd = 001 mix2_idd = 010 mix2_idd = 011 mix2_idd = 100 mix2_idd = 101 0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 250 500 750 1000 1250 1500 1750 noise figure (db) rf input frequency (mhz) mixer noise figure versus temperature & voltage if = 100mhz & mix2 _idd = 001 -40degc, +2.7v -40degc, +3.0v -40degc, +3.6v +27degc, +2.7v +27degc, +3.0v +27degc, +3.6v +85degc, +2.7v +85degc, +3.0v +85degc, +3.6v 0.0 5.0 10.0 15.0 20.0 25.0 30.0 250 500 750 1000 1250 1500 1750 2000 2250 input ip3 (dbm) rf input frequency (mhz) mixer input ip3 versus rf input frequency if = 100mhz & lo = rf - if +27degc and +3.0v supply mix2_idd = 001 mix2_idd = 010 mix2_idd = 011 mix2_idd = 100 mix2_idd = 101 8.0 8.5 9.0 9.5 10.0 10.5 11.0 -40-20 0 20406080100 nf (db) temperature (c) nf versus temperature and supply voltage (low noise mode mix2_idd=001) 2.7v 3.0v 3.6v -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 -40-20 0 20 40 60 80100 gain (db) temperature (c) gain versus temperature and supply voltage (excluding losses in pcb and baluns) 2.7v 3.0v 3.6v
8 of 36 RF2053 ds140110 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . typical performance characteristics for the RF2053 mixer v dd =3v, t a =25c, unless stated, as measured on RF2053 wideband evaluation board, phase detector frequency=26mhz 0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 250 500 750 1000 1250 1500 1750 2000 2250 pin 1db (dbm) rf input frequency (mhz) mixer input power for 1db compression if = 100mhz, +27degc & 3.0v supply mix2_idd = 001 mix2_idd = 010 mix2_idd = 011 mix2_idd = 100 mix2_idd = 101 0.0 5.0 10.0 15.0 20.0 25.0 30.0 001 010 011 100 101 input ip3 (dbm) mixer bias current setting (mix2_idd) mixer input ip3 versus temperature & voltage rf input frequency = 1000mhz & if = 100mhz -40degc, +2.7v -40degc, +3.0v -40degc, +3.6v +27degc, +2.7v +27degc, +3.0v +27degc, +3.6v +85degc, +2.7v +85degc, +3.0v +85degc, +3.6v 0.0 5.0 10.0 15.0 20.0 25.0 30.0 001 010 011 100 101 input ip3 (dbm) mixer bias current setting (mix2_idd) mixer input ip3 versus temperature & voltage rf input frequency = 2000mhz & if = 100mhz -40degc, +2.7v -40degc, +3.0v -40degc, +3.6v +27degc, +2.7v +27degc, +3.0v +27degc, +3.6v +85degc, +2.7v +85degc, +3.0v +85degc, +3.6v 0.0 10.0 20.0 30.0 40.0 50.0 60.0 70.0 0 500 1000 1500 2000 2500 rf to if isolation (db) rf input frequency (mhz) mixer rf input to if output isolation versus temperature and supply voltage if = 100mhz & lo = rf + if -40degc, +2.7v -40degc, +3.0v -40degc, +3.6v +27degc, +2.7v +27degc, +3.0v +27degc, +3.6v +85degc, +2.7v +85degc, +3.0v +85degc, +3.6v 6.0 8.0 10.0 12.0 14.0 16.0 250 500 750 1000 1250 1500 1750 2000 2250 pin 1db (dbm) rf input frequency (mhz) mixer input power for 1db compression versus temperature & voltage if = 100mhz & mix2_idd = 101 -40degc, +2.7v -40degc, +3.0v -40degc, +3.6v +27degc, +2.7v +27degc, +3.0v +27degc, +3.6v +85degc, +2.7v +85degc, +3.0v +85degc, +3.6v -80.0 -70.0 -60.0 -50.0 -40.0 -30.0 -20.0 -10.0 0.0 250 500 750 1000 1250 1500 1750 2000 2250 lo leakage (dbm) lo frequency (mhz) lo leakage in dbm at mixer if output versus temperature and supply voltage -40degc, +2.7v -40degc, +3.0v -40degc, +3.6v +27degc, +2.7v +27degc, +3.0v +27degc, +3.6v +85degc, +2.7v +85degc, +3.0v +85degc, +3.6v
9 of 36 RF2053 ds140110 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . detailed description the RF2053 is a wideband rf frequency converter chip which includ es a fractional-n phase-locked loop, a crystal oscillator cir- cuit, an lo buffer, and an rf mixer. the pll operates with an external vco. synthesizer programming, device configuration and control are achieved through a mixture of hardware and software controls. all on-chip registers are programmed through a sim- ple three-wire serial interface. vco the RF2053 has been designed for use with an external vc o. the vco inputs on pins 2 and 3 are differential. in order to route the vco input through buffers to the pll divi de circuits then cfg1:ext_vco must be set high and the vco control word must be set to vco3, pll2x0:p2_vcosel=10. the course tuning calibration (ct_cal) wh ich is not used by the RF2053 should be disabled in order to minimize the pll lock time. the vco signal can be divided by 1, 2, or 4 in the lo di vider circuit. the lo divide rati o is set by the pll2x0:p2_lodiv control words. for applications where the required lo frequency is above 2ghz it is recommended that the lo buffer current be increased by setting cfg5:lo2_i to 1100 (hex value c). fractional-n pll the ic contains a charge-pump based fractional-n phase locked loop (pll) for controlling the external vco. the pll is intended to use a reference frequency signal of 10mhz to 104mhz. a refe rence divider (divide by 1 to divide by 7) is supplied and should be programmed to limit the frequency at the phase detector to a maximum of 52mhz. the reference divider bypass is controlled by bit clk_div_byp, set low to enable the reference divider and set high for divider bypass (divide by 1). the remai n- ing three bits clk_div<15:13> set the reference divider value, divide by 2 (010) to 7 (111) when the reference divider is enabled. two pll programming banks are provided, the first bank is preceded by the label pll1 and the second bank is preceded by the label pll2. for the RF2053 the default programming bank is pll2, selected by setting the mode pin high. the pll will lock the vco to the frequency f vco according to: f vco =n eff *f osc /r where n eff is the programmed fractional n divider value, f osc is the reference input frequency, and r is the programmed r divider value (1 to 7). the n divider is a fractional divider, containing a dual-modulu s prescaler and a digitally spur-compensated fractional sequence generator to allow fine frequency steps. the n divide r is programmed using the n and num bits as follows: first determine the desired, effective n divider value, n eff : n eff =f vco *r/f osc n(9:0) should be set to the integer part of n eff . num should be set to the fractional part of n eff multiplied by 2 24 =16777216. example: vco operating at 2220mhz, 23.92mhz reference frequency, the desired effective divider value is: n eff =f vco *r / f osc =2220 *1 / 23.92=92.80936454895. the n value is set to 92, equal to the integer part of n eff , and the num value is set to the fractional portion of n eff multiplied by 2 24 : num=0.80936454895 * 2 24 =13,578,884. converting n and num into binary results in the following:
10 of 36 RF2053 ds140110 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . n = 0 0101 1100 num=1100 1111 0011 0010 1000 0100 so the registers would be programmed: p2_n = 0 0101 1100 p2_num_msb=1100 1111 0011 0010 p2_num_lsb=1000 0100 the maximum n eff is 511, and the minimum n eff is 15, when in fractional mode. the minimum step size is f osc /r*2 24 . thus for a 23.92mhz reference, the frequency step size would be 1. 4hz. the minimum reference frequency that can be used is sim- ply the maximum vco frequency required divided by 511. for example for a vco frequency of 2400mhz, the minimum refer- ence frequency, is 2400/511, 4.697mhz (approx). phase detector and charge pump the chip provides a current output to drive an external loop filter. an external low noise operational amplifier can be used to design an active loop filter or a passive design can be implemented. this depends on the tuning range of the external vco. the maximum charge pump output current is set by the value contained in the p2_cp_def field and cp_lo_i. in the default state (p2_cp_def=31 and cp_lo_i=0) the charge pump current (icpset) is 120ua. if cp_lo_i is set to 1 this current is reduced to 30ua. note that lowest phase noise within the loop bandwidth is achieved with the maximum charge pump current. the charge pump current can be altered by changing the value of p2_cp_def. the charge pump current is defined as: icp= icpset*cp_def / 31 changing the charge pump current will vary the loop filter response, higher current corresponding to a wider loop bandwidth. the phase detector will operate with a maximum input frequency of 52mhz. the loop filter calibration (kv_cal) is not us ed by the RF2053 and is disabled by default. loop filter the pll may be designed to use an active or a passive loop filter as required. the active loop filter uses an external low nois e op-amp. the cfg1:lf_act bit is set low in both cases so that the internal op-amp is disabled and a high impedance is pre- sented to the lfilt1 pin. the rf205x programming tool software can assist with loop filter designs. because the op-amp is used in an inverting configuration in acti ve mode, when the passive loop filter mode is selected the phase-detector polarity should be inverted. for active mode, cfg1:pdp=1, for passive mode, cfg1:pdp=0. the charge pump output voltage compliance range is typically +0.7v to +1.5v. for applications using a passive loop filter the required vco tuning voltage must fall within this voltage range under all conditions. when using an external op-amp as an inte- grator for the loop filter, as shown above, the non-inverting te rminal should be referenced to +1.1v. this holds the charge pump output at this voltage in the center of its compliance ra nge. the op-amp power supplies must be adequate to provide the necessary vco tuning voltage. + - lfilt1 RF2053 charge pump +1.1v typical active loop filter to vco tuning
11 of 36 RF2053 ds140110 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . crystal oscillator the pll may be used with an external reference source, or its own crystal oscillator. if an external source (such as a tcxo) is being used it should be ac-coupled into one of the xo in puts, and the other input should be ac-coupled to ground. a crystal oscillator typically takes many milliseconds to settle, and so for applications requiring rapid pulsed operation of t he pll (such as a tdma system, or rx/tx half -duplex system) it is necessary to keep the xo running between bursts. however, when the pll is used less frequently, it is desirable to turn off the xo to minimize current draw. the refstby register is pro- vided to allow for either mode of operation. if refstby is programmed high, the xo will continue to run even when enbl is asserted low. thus the xo will be stable and a clock is immediately available when enbl is asserted high, allowing the chip to assume normal operation. on cold start, or if refstby is programmed low, the xo will need a warm-up period before it can pro- vide a stable clock. the length of this warm-up peri od will be dependant on the crystal characteristics. the crystal oscillator circuit contains inte rnal loading capacitors. no external loading capacitors are required, dependant on the crystal loading specification. the internal loading capacitors are a combination of fixed capacitance, and an array of switched capacitors. the switched capacitors can be used to tune the crystal oscillat or onto the required center frequency and minimize frequency error. the pcb stray capacitance and oscillat or input and output capacitance will also contribute to the crystal?s total load capacitance. the regi ster settings in the cfg4 register for the switched capacitors are as follows: ? coarse tune xo_ct (4 bits) 15*0.55pf, default 0100 ? fine step xo_cr_s (1 bit) 1*0.25pf, default 0 the on chip fixed capacitance is approximately 4.2pf. wideband mixer the RF2053 includes a wideband, double-bal anced gilbert cell mixer. it supports rf/if frequencies of 30mhz to 2500mhz. the mixer has an input port and an output port that can be used for either if or rf, i.e. for up conversion or down conversion. the mixer current can be programmed to between 15ma and 35ma depending on linearity requirements, using the mix- 2_idd<3:0> word in the cfg2 register. the ma jority of the mixer current is sourced thro ugh the output pins via either a centre- tapped balun or an rf choke in the ex ternal matching circuitry to the supply. the rf mixer input and output ports are differential and require simple matching circuits optimi zed to the specific application frequencies. a conversion gain of approximately -3db to 0db is achieved with 100 ? differential input impedance, and the out- puts driving 200 ? differential load impedance. increasing the mixer output load increases the conversion gain. the mixer has a broadband common gate input. the input impe dance is dominated by the resistance set by the mixer 1/gm term, which is inversely proportional to the mixer cu rrent setting. the resistan ce will be approximately 85 ? at the default mixer current setting (100). there is also some shunt capacitance at the mixer input, and the inductance of the bond wires to con- sider at higher frequencies. the mixer output is high impedance, consisting of a resistance of approximately 2k ? in parallel with some capacitance. the mixer output does not need to be matched as such, just to see a resistive load. a higher resistance load will give higher outpu t voltage and gain. a shunt inductor can be used to resonate with the mixer output capacitance at the frequency of interest. this inductor may not be required at lower frequencies where the impe dance of the output capacitance is less significant. at higher output frequencies the inductance of th e bond wires becomes more significant. for more information about the mixer port impedances and matc hing, please refer to the rf205x family application note on matching circuits and baluns.
12 of 36 RF2053 ds140110 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . general programming information serial interface all on-chip registers in the RF2053 are progra mmed using a 3-wire serial bus which supports both write and read operations. synthesizer programming, device configuration and control are achieved through a mixture of hardware and software controls. certain functions and operations require the use of hardware controls via the enbl, mode, and resetb pins in addition to programming via the serial bus. for most applications the mode pin can be held high. serial data timing characteristics parameter description time t1 reset delay >5ns t2 programming setup time >5ns t3 programming hold time >5ns t4 enx setup time >5ns t5 enx hold time >5ns t6 data setup time >5ns t7 data hold time >5ns t8 enbl setup time >0ns t9 enbl hold time >0ns mcu enx sclk sdata enbl resetb mode 3-wire bus hardware controls RF2053 resetb enx sclk sdata enbl x reset chip initial programming of device programming updates serial bus x x x x x x x t1 t2 t3 t4 t5 t8 t6 t7 t9
13 of 36 RF2053 ds140110 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . write initially enx is high and sdata is high impedance. the write oper ation begins with the controller starting sclk. on the first f all- ing edge of sclk the baseband asserts enx lo w. the second rising edge of sclk is reserved to allow the sdi to initialize, and the third rising edge is used to define whether the operation will be a write or a read operation. in write mode the baseband w ill drive sdata for the entire telegram. RF2053 will re ad the data bit on the rising edge of sclk. the next 7 data bits are the register address, msb first. this is followed by the payload of 16 data bits for a total write mod e transfer of 24 bits. data is latched into RF2053 on the la st rising edge of sclk (a fter enx is asserted high). for more information, please refer to the timing diagram on page 12. the maximum clock speed for a register write is 19.2mhz. a re gister write therefore takes approximately 1.3us. the data is latched on the rising edge of the clock. th e datagram consists of a single start bit followed by a ?0? (to indicate a write ope ra- tion). this is then followed by a seven bit address and a sixteen bit data word. note that since the serial bus does not require the presence of the crystal clock, it is necessary to insert an additional risi ng clock edge before the enx line is set low to ensure the address/data are read correctly. read initially enx is high and sdata is high impedance. the read oper ation begins with the controller starting sclk. the controller is in control of the sdata line during the address write operation. on the first falling edge of sclk the baseband asserts enx low . the second rising edge of sclk is reserved to allow the sdi to initialize, and the third rising edge is used to define whether the operation will be a write or a read operation. in read mode the baseband will drive sdata for the address portion of the tele- gram, and then control will be handed over to RF2053 for the data portion. RF2053 will read the data bits of the address on the rising edge of sclk. after the address has been written, cont rol of the sdata line is handed over to RF2053. one and a half clocks are reserved for turn-around, and then the data bits ar e presented by RF2053. the data is set up on the rising edge of sclk, and the controller latches the data on the falling edge of sclk. at the end of the data transmissi on, RF2053 will release control of the sdata line, and the controller asserts enx high . the sdata port on RF2053 transitions from high impedance to low impedance on the first rising edge of the data portion of th e transaction (for example, 3 rising edges after the last addre ss bit has been read), so the controller chip should be presenting a high impedance by that time. for more information, please refer to the timing diagram on page 12. the maximum clock speed for a register read is 19.2mhz. a regi ster read therefore takes approximately 1.4us. the address is latched on the rising edge of the clock and the data output on the falling edge. the datagram co nsists of a single start bit fo l- a4 a3 a2 a1 a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 enx sclk sdata xa6 a5 a4 a3 a2 a1 a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 enx sclk sdata xa6 a5
14 of 36 RF2053 ds140110 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . lowed by a ?1? (to indicate a read operation), followed by a se ven bit address. a 1.5 bit delay is introduced before the sixtee n bit data word representing the register content is presented to the receiver. note that since the serial bus does not require the presence of the crystal clock, it is necessary to insert an additional risi ng clock edge before the enx line is set low to ensure the address is read correctly. hardware control three hardware control pins are provided: enbl, mode, and resetb. enbl pin the enbl pin has two functions: to enable the analog circuits in the chip and to trigger the pll to lock. every time the frequency of the synthesizer is re-programmed, enbl has to be taken high to initiate pll locking. resetb pin the resetb pin is a hardware reset control that will reset all digital circuits to th eir start-up state when asserted low. the device includes a power-on-reset function, so this pin should no t normally be required, in which case it should be connected to the positive supply. mode pin the mode pin controls which pll programming register bank is active. for normal operation of the RF2053 the mode pin should be set high to select the default pll2 programming registers. it is possible to set the fulld bit in the cfg1 register high. this allows the mode pin to select either pll1 register bank (mode=low) or pll2 register bank (mode=high). this may be useful for some applications where two lo frequencies can be programmed into the registers then the mode pin used to toggle between them. the enbl pin will also need to be cycled to re- lock the synthesizer for each frequency. enbl pin refstby bit xo and bias block analogue block digital block low 0 off off on low 1 on off on high0 ononon high1 ononon parameter description time t1 mode setup time >5ns t2 mode hold time >5ns enbl mode t1 t2
15 of 36 RF2053 ds140110 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . programming the RF2053 the figure below shows an overview of the device programming. note: the set-up processes 1 to 2, 2 to 3, and 3 to 4 are explained further below. additional information on device use and programming can be found on the rf 205x family page of the rfmd web site (http://www.rfmd.com/rf205x). the following documents may be particularly helpful: ? rf205x frequency synthesizer user guide ? rf205x calibration user guide device off set-up device operation set operating frequencies set calibration mode enable device apply power 1 2 3 4 reset device apply power to the device. ensure the device is set into a known and correct state. to use the device it will be necessary to program the registers with the desired contents to achieve the required operating characteristics. see following sections for details. when programming is complete the device can be enabled.
16 of 36 RF2053 ds140110 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . start-up when starting up and following device reset then refstby=0, refstby should be asserted high approximately 500ecs. before enbl is taken high. this is to allow the xo to settle and will depend on xo characteristics. after taking enbl high ther e is typically 20usecs for the pll state machine and charge pump to initialize, the vco warm-up state, before pll locking starts. the time spent in the vco warm-up state is set by cfg1:tvco, which should be set to 00111 when using a 26mhz clock. fol- lowing the warm-up period there wi ll be the additional time taken for the pll to settle to the required frequency. all of these timings will be dependent upon application specific factors such as loop filter bandwidth, reference clock frequency, and xo characteristics. the fastest turn-on and lock time will be obtained by leaving refstby asserted high, disabling all calibration routines (always the case for the RF2053), minimizing the vco warm-up time, and sett ing the pll loop bandwidth as wide as possible. the device can be reset into its initial state (default settings) at any time by performing a hard reset. this is achieved by s etting the resetb pin low for at least 100ns. setting up device operation the device offers a number of operating modes which need to be set up in the device before it will work as intended. this is achieved as follows. three registers need to be written, taking 3.9us at the maximum clock speed. set-up device operation active loop filter? default no pdp set to 0 program mix2_idd set-up com plete program xo_ct, xo_cr_s and clk_div internal capacitors used to set xtal load mixer linearity 1 2 to set up RF2053 operation with an external vco it is necessary to set the ext_vco bit in cfg1 register high and to always select vco3 to route the vco input through to the synthesizer. the lf_act bit in cfg1 register should be set to 0 as an external op-amp is normally used in the loop filter. the m ixer linearity setting is then selected. the default value is 4 with 1 being the lowest setting and 5 the highest. the m ix2_idd bits are located in the cfg 2 register. the internal crystal loading capacitors are also program m ed to present the correct load to the crystal. the capacitance internal to the chip can be varied from 8-16pf in 0.25pf steps (default=10pf). the reference divider m ust also be set to determ ine the phase detector frequency (default=1). these bits are located in the cfg4 register. program ext_vco=1 p2_vcosel=10 lf_act=0 w hen setting up the device it is necessary to decide if an active or passive loop filter will be used in the phase locked loop. set the phase detector polarity bit in cfg1 since the active filter inverts the loop filter voltage. norm ally active loop filter w ith an external op- amp is used with the RF2053, so set pdp = 1, the default setting.
17 of 36 RF2053 ds140110 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . disabling calibration the vco coarse tune calibration should be disabled as it is not used on the rf5203. the loop filter calibration, also unused, i s disabled by default. one register needs to be written taking 1.3us at maximum clock sp eed. since it is necessary to program this register when set- ting the operating frequency (see next section) this operation usually carries no overhead. p2_ct_en set to 00 set calibration mode operating mode set default disable loop filter calibration 2 3 disable coarse tune calibration. not required for the RF2053. the loop filter (kv) calibration is also not required for the RF2053. the default setting is for the loop filter calibration to be disabled so no programming is required for this step.
18 of 36 RF2053 ds140110 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . setting the operating frequency setting the operating frequency of the device requires a number of registers to be programmed. a total of four registers must be programmed to set the device operating frequency. this will take 5.2us for each path at maxi- mum clock speed. to change the frequency of the vco it will be necessary to repe at these operations. however, if the frequency shift is small it may not be necessary to reprogram all the bits reducing the number of register writes to three. for an example on how to determine the integer and fractional pa rts of the synthesizer pll divisi on ratio please refer to the detailed description of the pll on page 9. set operating frequencies program p2_lodiv and lo2_i program p2_n program p2_num_msb program p2_num_lsb frequency programmed 3 4 when programming the operating frequency it is necessary to select the appropriate lodiv value, located in the pll2x0 register. if the lo frequency is above 2ghz the lo path current (cfg5) should be set to 0xc. the integer part of the pll division ratio is programmed into the pll2x3 register. the msb of the fractional part of the synthesizer pll divider value is programmed into the pll2x1 register. the lsb of the fractional part of the synthesizer pll divider value is programmed into the pll2x2 register.
19 of 36 RF2053 ds140110 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . programming registers register map diagram reg. name r/w add data 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cfg1 r/w 00 ld_en ld_lev tvco pdp lf_act cpl ct_pol res ext_vco fulld cp_lo_i cfg2 r/w 01 mix1_idd mix1_vb mix2_idd mix2_vb res kv_rng nbr_ct_avg nbr_kv_avg cfg3 r/w 02 tkv1 tkv2 res fll_fact ct_cpolrefstby cfg4 r/w 03 clk_div_bypass xo_ct xo_i2 xo_i1 xo_cr_s tct cfg5 r/w 04 lo1_i lo2_i t_ph_algn cfg6 r/w 05 su_wait res pll1x0 r/w 08 p1_vcosel p1_ct_e n p1_kv_e n p1_lo- div res p1_cp_def pll1x1 r/w 09 p1_num_msb pll1x2 r/w 0a p1_num_lsb p1_ct_def res pll1x3 r/w 0b p1_n res p1_vcoi pll1x4 r/w 0c p1_dn p1_ct_gain p1_kv_gain res pll1x5 r/w 0d p1_n_phs_adj res p1_ct_v pll2x0 r/w 10 p2_vcosel p2_ct_e n p2_kv__e n p2_lo- div res p2_cp_def pll2x1 r/w 11 p2_num_msb pll2x2 r/w 12 p2_num_lsb p2_ct_def res pll2x3 r/w 13 p2_n res p2_vcoi pll2x4 r/w 14 p2_dn p2_ct_gain p2_kv_gain res pll2x5 r/w 15 p2_n_phs_adj res p2_ct_v gpo r/w 18 res p1_g- po1 res p1_ gpo 3 p1_ gpo 4 res p2_g- po1 res p2_g- po3 p2_ gpo 4 res chiprev r 19 partno revno rb1 r 1c lock ct_cal cp_cal res rb2 r 1d v0_cal v1_cal rb3 r 1e rsm_state res test r 1f ten tmux cpu cpd fnz ldo _by p tsel res dactest res
20 of 36 RF2053 ds140110 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . cfg1 (ooh) - operational configuration parameters cfg2 (o1h) - mixer bias and pll calibration # bit name default function 15 ld_en 1 9 enable lock detector circuitry 14 ld_lev 0 modify lock range for lock detector 13 tvco(4:0) 0 vco warm-up time=tvco/(f ref *256) 12 0 11 0 1 10 0 90 8 pdp 1 phase detector polarity: 0=positive, 1=negative 7 lf_act 1 c active loop filter enable, 1=active 0=passive 6 cpl(1:0) 1 charge pump leakage current: 00=no leakage, 01=low leakage, 10=mid leakage, 11=high leakage 50 4 ct_pol 0 polarity of vco coarse-tune word: 0=positive, 1=negative 300 2 ext_vco 0 set to 1=external vco (vco3 disabled, kv_cal and ct_cal must be disabled) 1 fulld 0 0=half duplex, mixer is enabled according to mode pin, 1=full duplex, both mixers enabled. for RF2053 setting fulld high gives access to both pll register banks using mode pin. 0 cp_lo_i 0 0=high charge pump current, 1=low charge pump current # bit name default function 15 mix1_idd 1 8 this register is not used for the RF2053. 14 0 13 0 12 mix1_vb 0 this register is not used for the RF2053. 11 1 c 10 mix2_idd 1 mixer 2 current setting: 000=0ma to 111=35ma in 5ma steps 90 80 7 mix2_vb 0 5 mixer 2 voltage bias 61 50 4 kv_rng 1 sets accuracy of voltage measurement during kv calibration: 0=8bits, 1=9bits 3 nbr_ct_avg 1 8 number of averages during ct cal 20 1 nbr_kv_avg 0 number of averages during kv cal 00
21 of 36 RF2053 ds140110 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . cfg3 (o2h) - pll calibration cfg4 (o3h) - crystal oscillator and reference divider # bit name default function 15 tkv1 0 0 settling time for first measurement in lo kv compensation 14 0 13 0 12 0 11 tkv2 0 4 settling time for second measurement in lo kv compensation 10 1 90 80 700 60 50 40 3 fll_fact 0 4 default setting 01. needs to be set to 00 for n<28. this case can arise when higher phase detector frequencies are used. 21 1ct_cpol 0 0 refstby 0 reference oscillator standby mode 0=xo is off in standby mode, 1=xo is on in standby mode # bit name default function 15 clk_div 0 1 reference divider, divide by 2 (010 ) to 7 (111) when reference divider is enabled 14 0 13 0 12 clk_div_bypass 1 reference divider enabled=0, divider bypass (divide by 1)=1 11 xo_ct 1 8 crystal oscillator coarse tune (approximately 0.5pf steps from 8pf to 16pf) 10 0 90 80 7 xo_i2 0 0 crystal oscillator current setting 6 xo_i1 0 5 xo_cr_s 0 crystal oscillator additional fixed capacitance (approximately 0.25pf) 4 tct 0 duration of coarse tune acquisition 31f 21 11 01
22 of 36 RF2053 ds140110 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . cfg5 (o4h) - lo bias cfg6 (o5h) - start-up timer # bit name default function 15 lo1_i 0 0 local oscillator path1 current setting 14 0 13 0 12 0 11 lo2_i 0 0 local oscillator path2 current setting 10 0 90 80 7 t_ph_algn 0 0 phase alignment timer 60 50 40 304 21 10 00 # bit name default function 15 su_wait 0 0 crystal oscillator settling timer. 14 0 13 0 12 0 11 0 1 10 0 90 81 700 60 50 40 300 20 10 00
23 of 36 RF2053 ds140110 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . pll1x0 (08h) - vco, lo divider and calibration select pll1x1 (09h) - msb of fr actional divider ratio # bit name default function 15 p1_vcosel 0 7 path 1 vco band select: 00=vco1, 01=vco2, 10=vco3, 11=reserved always set to 10 for vco3. 14 1 13 p1_ct_en 1 path 1 vco coarse tune: 00=disabled, 11=enabled set to 00 to disable vco coarse tune. 12 1 11 p1_kv_en 0 1 path 1 vco tuning gain ca libration: 00=disabled, 11=enabled set to 00 to disable calibration. 10 0 9 p1_lodiv 0 path 1 local oscillator divider: 00=divide by 1, 01=divide by 2, 10=divide by 4, 11=reserved 81 701 60 5 p1_cp_def 0 charge pump current setting if p1_kv_en=11 this value sets charge pump current during kv compensation only 41 31f 21 11 01 # bit name default function 15 p1_num_msb 0 6 path 1 vco divider numerator value, most significant 16 bits 14 1 13 1 12 0 11 0 2 10 0 91 80 707 61 51 41 306 21 11 00
24 of 36 RF2053 ds140110 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . pll1x2 (0ah) - lsb of fractional divider ratio and ct default pll1x3 (0bh) - integer divi der ratio and vco current # bit name default function 15 p1_num_lsb 0 2 path 1 vco divider numerator value, least significant 8 bits 14 0 13 1 12 0 11 0 7 10 1 91 81 7 p1_ct_def 0 7 path 1 vco coarse tuning value, not required for RF2053. 61 51 41 31e 21 11 00 # bit name default function 15 p1_n 0 2 path 1 vco divider integer value 14 0 13 1 12 0 11 0 3 10 0 91 81 700 60 50 40 302 2 p1_vcoi 0 path 1 vco bias setting: 000=minimum value, 111=maximum value 11 00
25 of 36 RF2053 ds140110 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . pll1x4 (0ch) - calibration settings pll1x5 (0dh) - more calibration settings # bit name default function 15 p1_dn 0 1 path 1 frequency step size used in vco tuning gain calibration 14 0 13 0 12 1 11 0 7 10 1 91 81 71e 6 p1_ct_gain 1 path 1 coarse tuning calibration gain 51 40 3 p1_kv_gain 0 4 path 1 vco tuning gain calibration gain 21 10 00 # bit name default function 15 p1_n_phs_adj 0 0 path 1 frequency step size used in vco tuning gain calibration 14 0 13 0 12 0 11 0 0 10 0 90 80 701 60 50 4 p1_ct_v 1 path 1 course tuning voltage setting when pe rforming course tuning calibration. not used by RF2053. 300 20 10 00
26 of 36 RF2053 ds140110 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . pll2x0 (10h) - vco, lo divider and calibration select pll2x1 (11h) - msb of fr actional divider ratio # bit name default function 15 p2_vcosel 0 7 path 2 vco band select: 00=vco1, 01=vco2, 10=vco3, 11=reserved. always set to 10 for vco3. 14 1 13 p2_ct_en 1 path 2 vco coarse tune: 00=disabled, 11=enabled. set to 00 to disable vco coarse tune. 12 1 11 p2_kv_en 0 1 path 2 vco tuning gain ca libration: 00=disabled, 11=enabled. set to 00 to disable calibration. 10 0 9 p2_lodiv 0 path 2 local oscillator divider: 00=divide by 1, 01=divide by 2, 10=divide by 4, 11=reserved 81 71 6 5 p2_cp_def 0 charge pump current setting. if p2_kv_en=11 this value sets charge pump current during kv compensation only 41 31f 21 11 01 # bit name default function 15 p2_num_msb 0 6 path 2 vco divider numerator value, most significant 16 bits 14 1 13 1 12 0 11 0 2 10 0 91 80 707 61 51 41 306 21 11 00
27 of 36 RF2053 ds140110 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . pll2x2 (12h) - lsb of fractional divider ratio and ct default pll2x3 (13h) - integer divider ratio and vco current # bit name default function 15 p2_num_lsb 0 2 path 2 vco divider numerator value, least significant 8 bits. 14 0 13 1 12 0 11 0 7 10 1 91 81 7 p2_ct_def 0 7 path 2 vco coarse tuning value. not required for RF2053. 61 51 41 31e 21 11 00 # bit name default function 15 p2_n 0 2 path 2 vco divider integer value 14 0 13 1 12 0 11 0 3 10 0 91 81 700 60 50 40 302 2 p2_vcoi 0 path 1 vco bias setting: 000=minimum value, 111=maximum value 11 00
28 of 36 RF2053 ds140110 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . pll2x4 (14h) - calibration settings pll2x5 (15h) - more calibration settings # bit name default function 15 p2_dn 0 1 path 2 frequency step size used in vco tuning gain calibration 14 0 13 0 12 1 11 0 7 10 1 91 81 71e 6 p2_ct_gain 1 path 2 coarse tuning calibration gain 51 40 3 p2_kv_gain 0 4 path 2 vco tuning gain calibration gain 21 10 00 # bit name default function 15 p2_n_phs_adj 0 0 path 2 synthesizer phase adjustment 14 0 13 0 12 0 11 0 0 10 0 90 80 701 60 50 4 p2_ct_v 1 path 2 course tuning voltage setting when pe rforming course tuning calibration. not used by RF2053. 300 20 10 00
29 of 36 RF2053 ds140110 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . gpo (18h) - internal control output settings chiprev (19h) - chip revision information # bit name default function 15 0 0 14 p1_gpo1 0 setting of gpo1 when path 1 is active, used internally only 13 0 12 p1_gpo3 0 setting of gpo3 when path 1 is active, used internally only 11 p1_gpo4 0 0 setting of gpo4 when path 1 is active, used internally only 10 0 90 80 700 6 p2_gpo1 0 setting of gpo1 when path 2 is active, used internally only 50 4 p2_gpo3 0 setting of gpo3 when path 2 is active, used internally only 3 p2_gpo4 0 0 setting of gpo4 when path 2 is active, used internally only 20 10 00 # bit name default function 15partno 00rfmd part number for device 14 0 13 0 12 0 11 0 0 10 0 90 80 7 revno x x part revision number 6x 5x 4x 3xx 2x 1x 0x
30 of 36 RF2053 ds140110 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . rb1 (1ch) - pll lock and calibration results read-back rb2 (1dh) - calibration results read-back # bit name default function 15 lock x x pll lock detector, not used by RF2053. 14 ct_cal x ct setting, not used by RF2053. 12 x 11 x x 10 x 9x 8x 7 cp_cal x x cp setting, not used by RF2053. 5x 4x 3xx 2x 10 00 # bit name default function 15 vo_cal x x the vco voltage measured at the start of a vco gain calibration. not used by RF2053. 14 x 13 x 12 x 11 x x 10 x 9x 8x 7 v1_cal x x the vco voltage measured at the end of a vco gain calibration. not used by RF2053. 6x 5x 4x 3xx 2x 1x 0x
31 of 36 RF2053 ds140110 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . rb3 (1eh) - pll state read-back test (1fh) - test modes # bit name default function 15 rsm_state x x state of the radio state machine 14 x 13 x 12 x 11 x x 10 x 90 80 700 60 50 40 300 20 10 00 # bit name default function 15ten 00enables test mode 14 tmux 0 sets test multiplexer state 13 0 12 0 11 cpu 0 0 set charge pump to pump up, 0=normal operation 1=pump down 10 cpd 0 set charge pump to pump down, 0=normal operation 1=pump down 9 fnz 0 0=normal operation, 1=fractional divider modulator disabled 8 ldo_byp 0 on chip low drop out regulator bypassed 7tsel 0 0 60 50 4 dactest 0 dac test 300 20 10 00
32 of 36 RF2053 ds140110 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . evaluation board the following diagrams show the schemati c and pcb layout of the RF2053 evaluation boards.the standard evaluation board, dk2053, has been configured with a narr owband vco covering 1646mhz to 1670 mhz. the wideband evaluation board, dk2053-wb, has a vco covering over an octave, 950mhz to 2150mh z. the mixer input and output on both boards have been configured for broadband oeration. application notes have been produced showing how the device is matched and on balun implementations for narrowband applications. the evaluation boards are provided as part of a design kit (dk2053 and dk2053-wb), along with the necessary cables and programming software tool to enable fu ll evaluation of the RF2053.
33 of 36 RF2053 ds140110 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . evaluation board schematic narrowband with umx-236-d16 vco 1 3 2 6 5 4 7 8 25 27 26 30 29 28 31 32 24 22 23 19 20 21 18 17 9 11 10 14 13 12 15 16 r1 51 k ? c5 33 pf c34 10 nf c35 33 pf enbl lfilt1 c36 33 pf mode c16 dni 26 mhz xtal c22 dni c7 dni j6 ref c3 33 pf c19 10 nf vddd c2 33 pf c18 10 nf vdda tc1-1-13m c23 100 pf t2 c24 100 pf c31 dni r15 0 r 50 ??? strip j2 rf ip l1 dni r8 dni t1 tc4-19+ c20 100 pf c21 100 pf c25 dni r14 0 r 50 ??? strip j1 rf op c29 100 nf c1 33 pf c13 33 pf c14 33 pf c15 33 pf sdata sclk enx resetb r3 100 k ? cb2 cb4 12 11 10 9 8 7 6 5 4 3 2 1 dsr# uio 13 14 15 16 17 18 19 20 21 22 23 24 cb0 cb1 vcc rst# cb3 pu1 pu2 vcc usb sld socket for usb interface 13 14 15 16 17 18 19 20 21 22 23 24 hdr_2x12 12 11 10 9 8 7 6 5 4 3 2 1 vdd vdd sclk enx resetb vdda enbl sdata vddd mode c12 10 uf c11 10 uf vdda c6 22 pf vdda indp indn vdd r7 10 k -v_op c10 100 nf +v_op c9 100 nf vdd_vco c43 10 nf 16 15 14 13 1 10 9 17 12 2 3 4 5 6 7 8 11 50 ??? strip 50 ? ? strip r22 18r r23 18r r24 dni 50 ? ? strip r25 dni 22 pf c41 c42 22 pf r21 18r 50 ??? strip j7 lo_op umx-236-d16 vco c39 22 pf c38 10 nf r18 0r vdd_vco c30 3.3 nf r2 1k r11 1k tp5 c27 3.3 nf vtune -v_op c4 10 nf r10 2.2k c28 100 nf r6 6.8k +v_op +1.2v tp4 filt1 c26 33 nf r9 1k5 c16 1.5 nf +v_op c8 10 nf active loop filter t5 tc1-1-13m v tune indp indn note: for the umx-236-d16 vco vdd_vco is +5vdc +v_op is +5vdc -v_op is -5vdc u1 opa27
34 of 36 RF2053 ds140110 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . wideband with ums-2150-r16 vco 1 3 2 6 5 4 7 8 25 27 26 30 29 28 31 32 24 22 23 19 20 21 18 17 9 11 10 14 13 12 15 16 r1 51 k ? c5 33 pf c34 10 nf c35 33 pf enbl lfilt1 c36 33 pf mode c16 dni 26 mhz xtal c22 dni c7 dni j6 ref c3 33 pf c19 10 nf vddd c2 33 pf c18 10 nf vdda tc1-1-13m c23 100 pf t2 c24 100 pf c31 dni r15 0 r 50 ??? strip j2 rf ip l1 dni r8 dni t1 tc4-19+ c20 100 pf c21 100 pf c25 dni r14 0 r 50 ??? strip j1 rf op c29 10 nf c1 33 pf c13 33 pf c14 33 pf c15 33 pf sdata sclk enx resetb r3 100 k ? cb2 cb4 12 11 10 9 8 7 6 5 4 3 2 1 dsr# uio 13 14 15 16 17 18 19 20 21 22 23 24 cb0 cb1 vcc rst# cb3 pu1 pu2 vcc usb sld socket for usb interface 13 14 15 16 17 18 19 20 21 22 23 24 hdr_2x12 12 11 10 9 8 7 6 5 4 3 2 1 vdd vdd sclk enx resetb vdda enbl sdata vddd mode c12 10 uf c11 10 uf vdda c6 33 pf vdda indp indn vdd r7 10 k -v_op c10 100 nf +v_op c9 100 nf vdd_vco c43 1 uf 16 15 14 13 1 10 9 17 12 2 3 4 5 6 7 8 11 lo c40 33 pf 50 ? ? strip r22 0r r23 68r r24 100r 50 ? ? strip r25 100r t5 tc1-1-13m 33 pf c41 c42 33 pf r21 68r 50 ? ? strip j7 lo_op ums-2150-r16 wideband vco 950 mhz to 2150 mhz c39 33 pf c38 10 nf r18 0r vdd_vco c30 6.8 nf r2 10r r11 120r tp5 c27 6.8 nf vtune -v_op c4 10 nf r10 680r c28 10 nf r6 10k +v_op +1.1v tp4 lfilt1 c26 22 nf r9 680r c17 1 nf +v_op c8 10 nf active loop filter u1 opa27 vdd_vco note: for the ums-2150-r16 vdd_vco is +12vdc +v_op is +16vdc -v_op is -5vdc indn indp v tune
35 of 36 RF2053 ds140110 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . evaluation board layout board size 2.5?x2.5? board thickness 0.040?, board material fr-4
36 of 36 RF2053 ds140110 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . package drawing qfn, 32-pin, 5mmx5mm support and applications information application notes and support material can be downlo aded from the product web page: www.rfmd.com/rf205x. ordering information part number package quantity RF2053 32-pin qfn 25pcs sample bag RF2053sb 32-pin qfn 5pcs sample bag RF2053sr 32-pin qfn 100pcs reel RF2053tr7 32-pin qfn 750pcs reel RF2053tr13 32-pin qfn 2500pcs reel dk2053 complete design kit narrowband vco evaluation board 1 box dk2053wb complete design kit wideband vco evaluation board 1 box 0.08 c 0.1 c -c- 0.850.10 detail ?d? rotated cw shaded area indicates pin 1. dimensions in mm. 0.00 0.05 seating plane -a- -b- 5.00 5.000 3.700.10 0.1 c m a b 1 0.25 typ. 0.1 c m a b 0.230.05 32x 1 0.1 c 0.850.10 see detail ?d? see detail ?d? 0.350.05 32x 0.50 typ.

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